Sink/Source DDR Termination Regulator, EUP7998 Replace RT9088.
EUP7998
EUP7998.pdf
EUP7998.pdfFEATURES
? VLDOIN Input Voltage Range: 1.1V to 3.5V
? VIN Input Voltage Range: 2.375V to 5.5V
? Typically 3×10μF MLCCs stable for DDR
? Fast Load-Transient Response
? ±10mA Buffered Reference (REFOUT)
? Meet DDR, DDR2 JEDEC Specifications.
Supports DDR3 and Low-Power DDR3/DDR4
VTT Applications
? Power-Good Window Comparator
? With Soft Start, UVLO and OCP
? Thermal Shutdown
? Available in 10-Pin 3mm×3mm TDFN and
SOP-8 (EP) packages
? RoHS Compliant and 100% Lead(Pb)-Free
Halogen-Free
PIN CONFIGUTION
優(yōu)勢(shì)替代
FEATURES
? VIN Input Voltage Range: 1.1V to 3.5V
? VCNTL Input Voltage Range: 2.9V to 5.5V
? Support Ceramic Capacitors
? Power Good Indicator
? 10mA Source/Sink Reference Output
? Meet DDRI, DDRII JEDEC Spec
? Support DDRIII, Low Power DDRIII/DDRIV VTT
Applications
? Soft-Start Function
? UVLO and OCP Protection
? Thermal Shutdown
PIN CONFIGUTION
